As the technology nodes shrink, in some integrated circuit (IC) designs, there has been a desire to replace the typical polysilicon gate electrode with a metal gate electrode to improve device performance with decreased feature sizes. One process of forming a metal gate structure is termed a “gate last” process in which the final gate structure is fabricated “last” which allows for a reduced number of subsequent processes, including high temperature processing, that must be performed after formation of the gate.
However, there are challenges to implement such features and processes in complementary metal-oxide-semiconductor (CMOS) fabrication. For example, in a “gate last” fabrication process, dishing in a metal gate electrode is generated after a metal chemical mechanical polishing (CMP) process, thereby increasing the likelihood of device instability and/or device failure.